Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories
DSP cores occupy a key role in System-on-Chips (SoCs) targeting a wide range of end products, from smartphones and wearable devices, to wireless infrastructure. Depending on the application, these core implementations may target high or low speeds but they always seek to optimize area and power dissipation. In this webinar, CEVA and Synopsys will present results and best practices in hardening DSP cores to achieve performance targets while consuming low power and using minimal area in target applications, using DesignWare® Logic Libraries and Memory Compilers on a 28-nm process, along with Synopsys' implementation and signoff tools. CEVA will also show how choosing the correct IP and methodology helps achieve optimal results and overcome physical design bottlenecks.
Attendees Will Learn:
- How optimized embedded memories and logic libraries can enable your DSP design to deliver required performance while keeping area and power consumption low
- How to select the correct design flow methodology to avoid physical design bottlenecks
- How to work your way out of design bottlenecks when your find out you’re in one