Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design

Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design

 

Available On Demand
Duration 60min
Speakers
Rita Horner
technical and product marketing manager
Synopsys
Rita Horner
Rita Horner has more than 20 years of experience in the area of mixed-signal circuit design, interconnect, test and packaging of high speed integrated circuits for consumer, computing, and high end networking ASSP and ASIC products. As a technical and product marketing manager, she has experience in ASSP, ASIC and Fiber Optic products, focusing on High Speed Serial Interconnect. She participated and presented in multiple standards bodies including ANSI T11, IEEE 802.3, OIF, and SFF Multi Souring Agreements.
Paul Hua
analog mixed-signal design manager
Synopsys
Paul Hua
Paul Hua is the analog mixed-signal design manager for Synopsys' SerDes IP products. Paul has over 22 years of experience in semiconductor industry, in which more than 12 of those years were spent in high speed analog mixed-signal R&D. Paul has designed, architected and managed a broad range of high speed SerDes products such as SATA/SAS, PCIe, USB, SONNET, CPRI/OBSAI, and Ethernet. Paul currently holds 11 patents in the area of analog, mixed-signal design.

Overview:
As the cost of IC design rapidly increases due to the reduction in feature sizes, companies are no longer designing products that target just a single application. Instead, ICs are architected to utilize multi-protocol PHY IP which can be connected to multiple different protocol-specific physical coded sub-layers and controllers. This augments the functionality of the device, enabling programmability and reducing the overall design cost. This webinar describes the design challenges addressed by a 12.5 Gbps PHY that supports a range of protocols and electrical specifications, all requiring different reference clock inputs, specific jitter requirements, and wide range of line rates.

Attendees will learn about the challenges of multi-protocol PHY IP in SoC design, and techniques to address these challenges, including:

  • Adaptive AFE, TX equalization, and DFE equalization to address the wide range of data rates
  • SSC range support, fractional PLLs, and reference clock repeaters to support a broad range of input reference clocks
  • Understanding and addressing jitter requirements of different protocols

Who Should Attend:
Design engineers, design managers, and system architects who are interested in implementing multi-protocol 12G SerDes IP into their SoCs

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