Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design
As the cost of IC design rapidly increases due to the reduction in feature sizes, companies are no longer designing products that target just a single application. Instead, ICs are architected to utilize multi-protocol PHY IP which can be connected to multiple different protocol-specific physical coded sub-layers and controllers. This augments the functionality of the device, enabling programmability and reducing the overall design cost. This webinar describes the design challenges addressed by a 12.5 Gbps PHY that supports a range of protocols and electrical specifications, all requiring different reference clock inputs, specific jitter requirements, and wide range of line rates.
Attendees will learn about the challenges of multi-protocol PHY IP in SoC design, and techniques to address these challenges, including:
- Adaptive AFE, TX equalization, and DFE equalization to address the wide range of data rates
- SSC range support, fractional PLLs, and reference clock repeaters to support a broad range of input reference clocks
- Understanding and addressing jitter requirements of different protocols
Who Should Attend:
Design engineers, design managers, and system architects who are interested in implementing multi-protocol 12G SerDes IP into their SoCs