Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP

 

Available On Demand
Duration 60min
Speakers
Hezi Saar
Product Marketing Manager for DesignWare MIPI IP
Synopsys
Hezi Saar
Hezi Saar serves as a staff product marketing manager at Synopsys and is responsible for its DesignWare® MIPI controller and PHY IP product line. He brings more than 15 years of experience in the semiconductor and electronics industries in embedded systems. Prior to joining Synopsys, Saar was responsible for Advanced Interface IP at Virage Logic that was acquired by Synopsys, from 2004 to 2009, Saar served as senior product marketing manager leading Actel's Flash field-programmable-gate-array (FPGA) product lines. Previously, he served as a product marketing manager at ISD/Winbond and as a senior design engineer at RAD Data Communications. Saar holds a Bachelor of Science degree from Tel Aviv University in computer science and economics and an MBA from Columbia Southern University.

Overview:
System-on-chips (SoCs) are offering higher performance, feature-rich applications, and higher quality multimedia content for mobile devices. These mobile multimedia devices require high-speed data transfers, and designers need to contend with pin count and channel limitations as well as bandwidth bottlenecks.

MIPI protocols based on the MIPI M-PHY are being adopted for storage and chip-to-chip connectivity to utilize the high performance and low power characteristics of the protocol and physical layer. This webinar provides an overview of the MIPI M-PHY and explains the integration challenges faced by designers while integrating M-PHY-based protocols into SoCs.

What attendees will learn:

  • MIPI M-PHY basics and advantages
  • A low-risk approach to designing a standard interface for storage and chip-to-chip connectivity
  • Trends in the mobile electronics market and problems that MIPI protocols solve
  • How to navigate existing and future protocols required in mobile electronics

Who should attend: SoC Design Engineers, ASIC Design Engineers, Designers of complex, high-performance systems, System architects and Engineering or Technical Managers

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