Reduce SoC Test Cost and Cut Weeks off Test Integration with Hierarchical Testing of all IP on a SoC

Reduce SoC Test Cost and Cut Weeks off Test Integration with Hierarchical Testing of all IP on a SoC


Available On Demand
Duration 60min
Sandeep Kaushik
Sr. Product Marketing Manager
Sandeep Kaushik
Sandeep Kaushik is the Sr. Product Marketing Manager for the Embedded Test and Repair product line at Synopsys. Sandeep brings over 13 years of experience in the field of Design-for-Test. Sandeep holds a Bachelor's Degree in Electrical Engineering from the Indian Institute of Technology in Delhi, India, a Master's Degree in Electrical Engineering from Stanford University and a Master's Degree in Business Administration from the Haas School of Business, University of California, Berkeley.

As designs become larger, there is a corresponding increase in the use of IP, making it difficult to complete testing of these large SoCs within the desired schedule and cost using traditional full-chip methodologies. The variety of IP blocks with different test interfaces on the SoC makes it extremely challenging and time-consuming to integrate and test all of the IP at the SoC level. A scalable hierarchical and area-efficient solution is required to meet today's SoC test needs. In this webinar we will describe how the DesignWare® STAR Hierarchical System leverages IP and logic block-level test and accelerate SoC testing by enabling faster design closure, and provides higher test quality and lower test cost with hierarchical testing of all IP including analog/mixed-signal IP, digital logic blocks, memory and interface IP.

What you will learn:

  • The technical trends and challenges associated with IP test and diagnostics in today's SoCs.
  • Solution for automatic IP test integration, pattern porting, flexible test scheduling and diagnostics
  • How Synopsys' DesignWare STAR Hierarchical System can meet your IP test, repair and diagnostics needs

Who should attend:
DFT engineers, test engineers, product engineers, IP developers, IP integration engineers, SoC architects, Designers.

Estimated length:
50 minutes, 10 minutes Q&A

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