Optimizing Quality-of-Service (QoS) with Interconnect and Memory Subsystem Analysis

Optimizing Quality-of-Service (QoS) with Interconnect and Memory Subsystem Analysis

 

Available On Demand
Duration 1h 0min
Speakers
Patrick Sheridan
Senior Staff Product Marketing Manager
Synopsys
Patrick Sheridan
Patrick Sheridan is responsible for Synopsys' system-level solution for multicore platform architecture design. In addition to his responsibilities at Synopsys, from 2005 through 2011 he served as the Executive Director of the Open SystemC Initiative (now part of the Accellera Systems Initiative). He has 30 years of experience in the marketing and business development of high technology hardware and software products and a BS in Computer Engineering from Iowa State University.
Tim Kogel
Solution Architect
Synopsys
Tim Kogel
Tim Kogel received his diploma and PhD degree in electrical engineering with honors from Aachen University of Technology (RWTH), Aachen, Germany, in 1999 and 2005 respectively. He has authored a book and numerous technical and scientific publications on electronic system-level design of multi-processor system-on-chip platforms. Today, he is working as a Solution Architect at Synopsys Inc. In this position, he is responsible for the product definition and future direction of Synopsys' SystemC-based Platform Architect product line.
Alexis Boutillier
Senior Corporate Application Engineer
Arteris
Alexis Boutillier
Alexis Boutillier has been working on network-on-chip (NoC) technologies for more than 10years. He developed a deep knowledge of on-chip interconnect solutions by participating in the engineering development of the first and second generations of Arteris network-on-chip products. Today, he is using his extensive knowledge of auto-generated System Verilog test benches and SystemC models to support the worldwide team of Field Application Engineers at Arteris and ensure the smooth integration with third-party tools.
 
Kris Keach
Contributing Editor
TechOnline
Kris Keach

Understanding how on-chip interconnect and DDR memory controller configurations impact the system performance, power and cost of multicore SoCs requires deep visibility. Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with the deep, system-level analysis they need to configure and optimize Quality-of-Service (QoS) features earlier in the design cycle.

We review best practices for analyzing and optimizing the on-chip interconnect and DDR controller configuration together to meet performance goals, including how to visualize multicore application deadlines, analyze data flow between all initiators and memory, and understand how application performance is sensitive to specific QoS settings. Featuring Synopsys Platform Architect MCO and IP solutions from Synopsys and Arteris, the tools and techniques demonstrated in this webinar have been shown to enable more optimal interconnect and DDR controller configuration to improve memory bandwidth, optimize QoS, and avoid the risk of over-design.

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